The metal-oxide-semiconductor (MOS) is a dominating technology for integrated circuits at 90 nm technology and beyond. A MOS device can work in three regions, depending on gate voltage Vg and source-drain voltage Vds, linear, saturation, and sub-threshold regions. The sub-threshold region is a region where Vg is smaller than the threshold voltage Vt. The sub-threshold swing represents the easiness of switching the transistor current off and thus is an important factor in determining the speed of a MOS device. The sub-threshold swing can be expressed as a function of m*kT/q, where m is a parameter related to capacitance. The sub-threshold swing of a typical MOS device has a limit of about 60 mV/decade (kT/q) at room temperature, which in turn sets a limit for further scaling of operation voltage VDD and threshold voltage Vt. This limitation is due to the drift-diffusion transport mechanism of carriers. For this reason, existing MOS devices typically cannot switch faster than 60 mV/decade at room temperatures. The 60 mV/decade sub-threshold swing limit also applies to FinFET or ultra thin-body MOSFET on silicon-on-insulator (SOI) devices. However, even with better gate control over the channel, an ultra thin body MOSFET on SOI or FinFET can only achieve close to, but not below, the limit of 60 mV/decade. With such a limit, faster switching at low operation voltages for future nanometer devices cannot be achieved.
To solve the above-discussed problem, tunnel field-effect transistors (FET) have been explored. FIG. 1 illustrates a FET device formed of a p-i-n diode called the I-MOS (impact-ionization MOS). The I-MOS has a heavily doped p-type (source) region 10 and a heavily doped n-type (drain) region 12 separated by an intrinsic channel region 14. Gate 16 is formed over the intrinsic channel region 14 to control the intrinsic channel region 14. The I-MOS has an offset region 18 between source region 10 and edge 11 of gate 16. When the intrinsic channel region 14 is inverted by the gate bias applied to gate 16, the drain-source voltage drops mainly across the offset region 18 and triggers an avalanche breakdown. The “avalanche multiplication” during breakdown serves as an internal positive feedback, so that the sub-threshold swing can be at a value less than 10 mV/decade at a very low drain voltage (for example, 0.2V). Such an I-MOS offers a promising approach for future MOS technology at 45 nm node and below due to the low power usage, high switching speed, and high on-current to off-current ratio.
The I-MOS shown in FIG. 1 suffers from some drawbacks, however. The output characteristics have large drain-to-source voltage dependence. Further, although it is capable of ultra-fast switching by avalanche mechanism, the critical width of the offset region 18 is sensitive to alignment errors between the gate and the source/drain. This leads to large variations of electrical fields in the offset region 18 during switching, which in turn leads to large variations of the sub-threshold swing. Furthermore, the avalanche mechanism of the I-MOS device is temperature sensitive, and temperature variations also lead to variations in sub-threshold swing.
FIG. 2 illustrates an asymmetric tunnel FET device formed of gated p-i-n diode, which includes a heavily doped drain region 102 and a heavily doped source region 104 separated by channel region 103. Drain region 102 comprises silicon, while source region 104 comprises silicon germanium. The channel region 103 is formed of intrinsic silicon. Gate 108 controls channel region 103. The tunnel FET device shown in FIG. 2 has a kT/q independent sub-threshold swing and a low off-state current. However, such a structure can only improve the on-currents of n-channel tunnel FET devices, while the on-currents of p-channel tunnel FET devices are not improved.
What is needed in the art, therefore, is a tunnel FET structure providing a high on current, a low off-current, and a reliable performance for both p-channel and n-channel tunnel FET devices.